Re: [PATCH 2/2] tests/tcg/riscv64: add misa write test

On Thu, 2026-08-06 at 16:37 +0300, Vladimir Isaev wrote:
> Add test to check that writing misa before compact instruction
> doesn't
> drop any bits.
> 
> Signed-off-by: Vladimir Isaev <[email protected]>

Reviewed-by: Alistair Francis <[email protected]>

Alistair

> ---
>  tests/tcg/riscv64/Makefile.softmmu-target |  4 ++
>  tests/tcg/riscv64/test-misa-w.S           | 46
> +++++++++++++++++++++++
>  2 files changed, 50 insertions(+)
>  create mode 100644 tests/tcg/riscv64/test-misa-w.S
> 
> diff --git a/tests/tcg/riscv64/Makefile.softmmu-target
> b/tests/tcg/riscv64/Makefile.softmmu-target
> index 82be8a2c91..e7d052909f 100644
> --- a/tests/tcg/riscv64/Makefile.softmmu-target
> +++ b/tests/tcg/riscv64/Makefile.softmmu-target
> @@ -41,5 +41,9 @@ comma:= ,
>  run-test-crc32: test-crc32
>  	$(call run-test, $<, $(QEMU) -cpu rv64$(comma)xlrbr=true
> $(QEMU_OPTS)$<)
>  
> +EXTRA_RUNS += run-test-misa-w
> +run-test-misa-w: test-misa-w
> +	$(call run-test, $<, $(QEMU) -cpu rv64$(comma)x-misa-
> w=true$(comma)c=true $(QEMU_OPTS)$<)
> +
>  # We don't currently support the multiarch system tests
>  undefine MULTIARCH_TESTS
> diff --git a/tests/tcg/riscv64/test-misa-w.S
> b/tests/tcg/riscv64/test-misa-w.S
> new file mode 100644
> index 0000000000..22cba98b8c
> --- /dev/null
> +++ b/tests/tcg/riscv64/test-misa-w.S
> @@ -0,0 +1,46 @@
> +#define MISA_C (1<<2)
> +
> +	.text
> +	.globl _start
> +	.balign 4
> +_start:
> +	.option norvc
> +	lla t0, trap
> +	csrw mtvec, t0
> +
> +	# Fail if misa after write is not the same as before
> +	csrr t0, misa
> +	.option rvc
> +	c.nop
> +	csrw misa, t0
> +	c.nop
> +	csrr t1, misa
> +	bne t0, t1, fail
> +
> +	li a0, 0
> +	j  _exit
> +
> +
> +	.balign 4
> +	.option norvc
> +trap:
> +fail:
> +	li	a0, 1
> +_exit:
> +	lla	a1, semiargs
> +	li	t0, 0x20026	# ADP_Stopped_ApplicationExit
> +	sd	t0, 0(a1)
> +	sd	a0, 8(a1)
> +	li	a0, 0x20	# TARGET_SYS_EXIT_EXTENDED
> +
> +	# Semihosting call sequence
> +	.balign	16
> +	slli	zero, zero, 0x1f
> +	ebreak
> +	srai	zero, zero, 0x7
> +	j	.
> +
> +	.data
> +	.balign	16
> +semiargs:
> +	.space	16