[PATCH v2 0/2] Fix alignment check for misa write

Vladimir Isaev <[email protected]>
Newsgroups org.nongnu.qemu-riscv,org.nongnu.qemu-devel
Message-ID <[email protected]>
Current version disable misa.C on misa write when next instruciton is
not aligned, fix it and add test.

Changes from v1:
  - Use the test from https://lore.kernel.org/r/[email protected],
    since it is much more comprehensive than mine.
  - Add GUEST_ERROR_LOG on a bad write attempt.

Vladimir Isaev (2):
  riscv: csr: do not drop C bit on misa write
  tests/tcg/riscv64: add misa write test

 target/riscv/tcg/csr.c                    | 10 ++-
 tests/tcg/riscv64/Makefile.softmmu-target |  4 ++
 tests/tcg/riscv64/test-misa-w.S           | 88 +++++++++++++++++++++++
 3 files changed, 99 insertions(+), 3 deletions(-)
 create mode 100644 tests/tcg/riscv64/test-misa-w.S

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2.55.0
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