Re: [PATCH] ARM: dts: aspeed-g6: add pcie-lpc and pcie-kcs4

On Mon, 2026-07-20 at 18:31 +0200, Gr=C3=A9goire Layet wrote:
> > > diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi b/arch/arm/boot/=
dts/aspeed/aspeed-g6.dtsi
> > > index 56bb3b0444f7..ac351f01048f 100644
> > > --- a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi
> > > +++ b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi
> > > @@ -658,6 +658,21 @@ ibt: ibt@140 {
> > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 };
> > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 };
> > >=20
> > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 pcie_lpc: pcie-lpc@1=
e789800 {
> >=20
> > lpc@1e789000 already maps 0x1e789000-0x1e78a000 and 0x1e789914 falls in=
side it,
>=20
> I agree that there is an overlap in address space in my patch.
> I will fix this in a new revision.
>=20
> > so you're describing a second `ast2600-lpc-v2` node which is unnecessar=
y.
> >=20
> > Suggestion: Merge pcie_kcs4 into lpc@1e789000 and use 914 as offset. Th=
at way
> > you don't accidentally cause an overlap for the devices if you describe=
 more in
> > the future.
>=20
> The 'kcs_bmc_aspeed' driver has the kcs channels address hard-coded.
> If the 'reg' property does not contain the three addresses used by one
> of the four channels, the driver returns -EINVAL.
> So having a pcie-kcs4 with regs 0x914, 0x918 and 0x91c doesn't work.

It does work if you fix the driver to allow it.

>=20
> This is why a second LPC node was added, for the pcie-kcs4 to have
> regs 0x114, 0x118 and 0x11c;
>=20
> I know we should write device tree sources based on hardware rather
> than around driver limitations.
> Changing how the driver behaves seems excessive for supporting KCS over P=
CIe.

I don't think this is true.

> I think a point can be made that the LPC over PCIe is a different LPC bus=
.

In my opinion it's most helpful if Table 8 in the datasheet is used as
the reference for address ranges in the devicetree. With that in mind,
I don't intend to apply a patch adding a new node as you've proposed. I
suggest adjusting the driver to identify the X{{I,O}D,ST}R4 addresses
as channel 4, under the existing LPC node as Tan suggested.

Andrew