Re: [PATCH v2 2/3] phy: add AST2700 usb3.2 phy driver

On Wed, 2026-07-15 at 05:55 +0000, Ryan Chen wrote:
>=20
> >=20
> > > +	}
> > > +
> > > +	/* Wait for USB3 PHY internal SRAM initialization done */
> > > +	ret =3D readl_poll_timeout(aspeed_phy->regs + PHY3S00, val,
> > > +				 val & PHY3S00_INIT_DONE,
> > > +				 USEC_PER_MSEC, 10 * USEC_PER_MSEC);
> > > +	if (ret) {
> > > +		dev_err(aspeed_phy->dev, "SRAM init timeout\n");
> > > +		goto err_assert_reset;
> > > +	}
> > > +
> > > +	val =3D readl(aspeed_phy->regs + PHY3S00);
> > > +	val |=3D PHY3S00_SRAM_BYPASS;
> > > +	writel(val, aspeed_phy->regs + PHY3S00);
> >=20
> > According to the datasheet PHY3S00[15] (PHY3S00_INIT_DONE above)
> > indicates that the PHY internal SRAM initialisation is complete. The da=
tasheet
> > reports the SRAM is used for configuration of calibration among other t=
hings.
> > PHY3S00[6] instructs the PHY that software has completed loading the
> > configuration data into SRAM, however PHY3S00_SRAM_BYPASS (PHY3S00[7])
> > tells the PHY to load configuration from "hard wired" values.
> >=20
> > Is it necessary to wait for SRAM initialisation to complete if we're by=
passing it?
> > Or are there other side-effects involved in the setting of PHY3S00[15]?
>=20
> Yes, it is necessary to wait SRAM initial, the driver polls PHY3S00[15].
> It reports that the boot loader in the PCS has finished initialising the=
=20
> SRAM (loading the contents into the PCS), and that initialisation has
> to complete before sram_bypass (PHY3S00[7]) may be asserted.=20
>=20

Can you improve the comment then to make it clear that the wait is
necessary despite the bypass?

Andrew