[PATCH u-boot v3 1/2] clk: ast2600: set default clk-delay for all ethernet macs to 0
Anirudh Srinivasan <[email protected]>
| Newsgroups | org.ozlabs.lists.openbmc |
|---|---|
| Message-ID | <[email protected]> |
u-boot currently setups non zero values for the ethernet mac clk delays. This is not always needed (depending on the board design), and prevents us from using rgmii-id as the phy mode in u-boot and linux. u-boot already has the funationality to read and use values for the clk delays from the DT, so based on the discussion here [1], update the default values for these clk delays to be zero instead. Also update the DTs for 3 existing boards to add scu nodes with the existing default value for the clk delay. ast2600-fpga and msx4-bmc use mac0 for networking, so that particular clk-delay value was added. ast2600-slt uses all 4 macs, so all 4 clk-delay values were added. Newly added boards that require no clk delays can use rgmii-id mode directly, and boards that actually require a clk delay can set it via the scu DT node. [1] https://lore.kernel.org/openbmc/a7d364d72bbfa4ed3d41e9f7282f8e87a783cf48.camel@codeconstruct.com.au/ Signed-off-by: Anirudh Srinivasan <[email protected]> --- The fpga and slt DTs don't seem to have the DT nodes sorted in any order, so I added the scu nodes at the end of those files. Setting a non-zero clk delay for the msx4 BMC device with rgmii-id as the phy mode feels wrong. But that's the current state of the tree (DT + default value of clk delay), so I've kept it as is. Ender, Marc, would it be possible for someone from nvidia to test this on the mx4 platform? Should we test this on the aspeed fpga and slt platforms too? Would someone from aspeed be able to do this? --- arch/arm/dts/ast2600-fpga.dts | 6 +++++ arch/arm/dts/ast2600-msx4-bmc-nvidia.dts | 6 +++++ arch/arm/dts/ast2600-slt.dts | 15 +++++++++++ drivers/clk/aspeed/clk_ast2600.c | 45 +++++++++++++------------------- 4 files changed, 45 insertions(+), 27 deletions(-) diff --git a/arch/arm/dts/ast2600-fpga.dts b/arch/arm/dts/ast2600-fpga.dts index 68ff64169ccd3f4c595aa043844db91a2bb3b18e..4c34bef32dca184a203e3e5c209da0a4b31af499 100644 --- a/arch/arm/dts/ast2600-fpga.dts +++ b/arch/arm/dts/ast2600-fpga.dts @@ -110,3 +110,9 @@ status = "okay"; }; + +&scu { + mac0-clk-delay = <0x10 0x0a + 0x10 0x10 + 0x10 0x10>; +}; diff --git a/arch/arm/dts/ast2600-msx4-bmc-nvidia.dts b/arch/arm/dts/ast2600-msx4-bmc-nvidia.dts index 9df5e74c98f4b6ccc74f93dd96fd4d6bb1b787ad..addd13fb05b1b7656f3e933a19a5dde0bb11eb0f 100644 --- a/arch/arm/dts/ast2600-msx4-bmc-nvidia.dts +++ b/arch/arm/dts/ast2600-msx4-bmc-nvidia.dts @@ -82,6 +82,12 @@ }; }; +&scu { + mac0-clk-delay = <0x10 0x0a + 0x10 0x10 + 0x10 0x10>; +}; + &sdrammc { clock-frequency = <400000000>; aspeed,ecc-enabled; diff --git a/arch/arm/dts/ast2600-slt.dts b/arch/arm/dts/ast2600-slt.dts index 332620dc1aece1f5ab7d4c130bc8fe31e324d56e..9e86dc271eaa42a86f4c6c4ee805bd975c9e2a11 100644 --- a/arch/arm/dts/ast2600-slt.dts +++ b/arch/arm/dts/ast2600-slt.dts @@ -280,3 +280,18 @@ &ehci1 { status = "okay"; }; + +&scu { + mac0-clk-delay = <0x10 0x0a + 0x10 0x10 + 0x10 0x10>; + mac1-clk-delay = <0x10 0x0a + 0x10 0x10 + 0x10 0x10>; + mac2-clk-delay = <0x08 0x04 + 0x08 0x04 + 0x08 0x04>; + mac3-clk-delay = <0x08 0x04 + 0x08 0x04 + 0x08 0x04>; +}; diff --git a/drivers/clk/aspeed/clk_ast2600.c b/drivers/clk/aspeed/clk_ast2600.c index d4fda1b231303041fe649df16eafae638fc77c8b..42295a2c6b4c1ea559906688b318755d3cb6e16a 100644 --- a/drivers/clk/aspeed/clk_ast2600.c +++ b/drivers/clk/aspeed/clk_ast2600.c @@ -58,30 +58,21 @@ #define RGMII12_CLK_OUTPUT_DELAY_PS 1000 #define RGMII34_CLK_OUTPUT_DELAY_PS 1600 -#define MAC_DEF_DELAY_1G FIELD_PREP(MAC_CLK_1G_OUTPUT_DELAY_1, 16) | \ - FIELD_PREP(MAC_CLK_1G_INPUT_DELAY_1, 10) | \ - FIELD_PREP(MAC_CLK_1G_OUTPUT_DELAY_2, 16) | \ - FIELD_PREP(MAC_CLK_1G_INPUT_DELAY_2, 10) -#define MAC_DEF_DELAY_100M FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_1, 16) | \ - FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_1, 16) | \ - FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_2, 16) | \ - FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_2, 16) -#define MAC_DEF_DELAY_10M FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_1, 16) | \ - FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_1, 16) | \ - FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_2, 16) | \ - FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_2, 16) -#define MAC34_DEF_DELAY_1G FIELD_PREP(MAC_CLK_1G_OUTPUT_DELAY_1, 8) | \ - FIELD_PREP(MAC_CLK_1G_INPUT_DELAY_1, 4) | \ - FIELD_PREP(MAC_CLK_1G_OUTPUT_DELAY_2, 8) | \ - FIELD_PREP(MAC_CLK_1G_INPUT_DELAY_2, 4) -#define MAC34_DEF_DELAY_100M FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_1, 8) | \ - FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_1, 4) | \ - FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_2, 8) | \ - FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_2, 4) -#define MAC34_DEF_DELAY_10M FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_1, 8) | \ - FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_1, 4) | \ - FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_2, 8) | \ - FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_2, 4) +#define MAC_DEF_DELAY_1G \ + FIELD_PREP(MAC_CLK_1G_OUTPUT_DELAY_1, 0) | \ + FIELD_PREP(MAC_CLK_1G_INPUT_DELAY_1, 0) | \ + FIELD_PREP(MAC_CLK_1G_OUTPUT_DELAY_2, 0) | \ + FIELD_PREP(MAC_CLK_1G_INPUT_DELAY_2, 0) +#define MAC_DEF_DELAY_100M \ + FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_1, 0) | \ + FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_1, 0) | \ + FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_2, 0) | \ + FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_2, 0) +#define MAC_DEF_DELAY_10M \ + FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_1, 0) | \ + FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_1, 0) | \ + FIELD_PREP(MAC_CLK_100M_10M_OUTPUT_DELAY_2, 0) | \ + FIELD_PREP(MAC_CLK_100M_10M_INPUT_DELAY_2, 0) /* * SCU 320 & 330 Frequency counters @@ -977,9 +968,9 @@ static u32 ast2600_configure_mac34_clk(struct ast2600_clk_priv *priv, struct ude u32 reg[3]; int ret; - reg[0] = MAC34_DEF_DELAY_1G; - reg[1] = MAC34_DEF_DELAY_100M; - reg[2] = MAC34_DEF_DELAY_10M; + reg[0] = MAC_DEF_DELAY_1G; + reg[1] = MAC_DEF_DELAY_100M; + reg[2] = MAC_DEF_DELAY_10M; ret = ast2600_find_dly32_tap(RGMII34_CLK_OUTPUT_DELAY_PS, priv->dly32_lookup[1]); if (ret > 0) { -- 2.52.0