From: Alice Guo <[email protected]>
Add a 900MHz rate entry to the fractional PLL table so that the required
clock frequency can be configured to support DDR at 3600MTS.
Signed-off-by: Alice Guo <[email protected]>
Signed-off-by: Ye Li <[email protected]>
---
arch/arm/mach-imx/imx9/clock.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c
index 4ccff67b7ab..4b89ee3b2b4 100644
--- a/arch/arm/mach-imx/imx9/clock.c
+++ b/arch/arm/mach-imx/imx9/clock.c
@@ -33,6 +33,7 @@ static struct imx_intpll_rate_table imx9_intpll_tbl[] = {
static struct imx_fracpll_rate_table imx9_fracpll_tbl[] = {
FRAC_PLL_RATE(1000000000U, 1, 166, 4, 2, 3), /* 1000Mhz */
FRAC_PLL_RATE(933000000U, 1, 155, 4, 1, 2), /* 933Mhz */
+ FRAC_PLL_RATE(900000000U, 1, 150, 4, 0, 1), /* 900Mhz */
FRAC_PLL_RATE(800000000U, 1, 200, 6, 0, 1), /* 800Mhz */
FRAC_PLL_RATE(700000000U, 1, 145, 5, 5, 6), /* 700Mhz */
FRAC_PLL_RATE(600000000U, 1, 200, 8, 0, 1), /* 600Mhz */
--
2.34.1
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