From: Ye Li <[email protected]>
During DDR PHY training, an intermediate 1800MTS data rate is also
exercised, which corresponds to a 450MHz DDR PLL frequency. Add this
rate to the DDR PLL table so the training sequence can program it.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Alice Guo <[email protected]>
---
arch/arm/mach-imx/imx9/clock.c | 1 +
drivers/ddr/imx/phy/ddrphy_utils.c | 4 ++++
2 files changed, 5 insertions(+)
diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c
index 4b89ee3b2b4..cc0a7729d94 100644
--- a/arch/arm/mach-imx/imx9/clock.c
+++ b/arch/arm/mach-imx/imx9/clock.c
@@ -40,6 +40,7 @@ static struct imx_fracpll_rate_table imx9_fracpll_tbl[] = {
FRAC_PLL_RATE(484000000U, 1, 121, 6, 0, 1),
FRAC_PLL_RATE(445333333U, 1, 167, 9, 0, 1),
FRAC_PLL_RATE(466000000U, 1, 155, 8, 1, 3), /* 466Mhz */
+ FRAC_PLL_RATE(450000000U, 1, 150, 8, 0, 1), /* 450Mhz */
FRAC_PLL_RATE(400000000U, 1, 200, 12, 0, 1), /* 400Mhz */
FRAC_PLL_RATE(300000000U, 1, 150, 12, 0, 1),
FRAC_PLL_RATE(233000000U, 1, 174, 18, 3, 4), /* 233Mhz */
diff --git a/drivers/ddr/imx/phy/ddrphy_utils.c b/drivers/ddr/imx/phy/ddrphy_utils.c
index 8e350de8315..665d32284ec 100644
--- a/drivers/ddr/imx/phy/ddrphy_utils.c
+++ b/drivers/ddr/imx/phy/ddrphy_utils.c
@@ -140,6 +140,10 @@ void ddrphy_init_set_dfi_clk(unsigned int drate)
dram_pll_init(MHZ(466));
dram_disable_bypass();
break;
+ case 1800:
+ dram_pll_init(MHZ(450));
+ dram_disable_bypass();
+ break;
case 1600:
dram_pll_init(MHZ(400));
dram_disable_bypass();
--
2.34.1
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