[PATCH] clk: qcom: sc7280: add SDCC2 apps clock support

Add the SDCC2 apps clock used by the external SD card port on sc7280.
The frequency table covers the standard SD rates up to 202 MHz.

The 202 MHz rate sources from GPLL9, which the earlier boot stages
leave disabled. Vote GPLL9 on before programming the RCG whenever the
selected frequency uses it, reusing clk_enable_gpll0() with a GPLL9
vote descriptor.

Signed-off-by: Balaji Selvanathan <[email protected]>
---
 drivers/clk/qcom/clock-sc7280.c | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/drivers/clk/qcom/clock-sc7280.c b/drivers/clk/qcom/clock-sc7280.c
index 91e3fcc27cb..8005946d713 100644
--- a/drivers/clk/qcom/clock-sc7280.c
+++ b/drivers/clk/qcom/clock-sc7280.c
@@ -27,6 +27,10 @@
 #define UFS_PHY_ICE_CORE_CLK_CMD_RCGR 0x7706c
 #define UFS_PHY_PHY_AUX_CLK_CMD_RCGR 0x770a0
 #define UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR 0x77084
+#define SDCC2_APPS_CLK_CMD_RCGR 0x1400c
+
+#define APCS_GPLL9_STATUS 0x1c000
+#define APCS_GPLLX_ENA_REG 0x52010
 
 static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
 	F(66666667, CFG_CLK_SRC_GPLL0_EVEN, 4.5, 0, 0),
@@ -85,6 +89,23 @@ static const struct freq_tbl ftbl_gcc_ufs_phy_unipro_core_clk_src[] = {
 	{ }
 };
 
+static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
+	F(400000, CFG_CLK_SRC_CXO, 12, 1, 4),
+	F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
+	F(25000000, CFG_CLK_SRC_GPLL0_EVEN, 12, 0, 0),
+	F(50000000, CFG_CLK_SRC_GPLL0_EVEN, 6, 0, 0),
+	F(100000000, CFG_CLK_SRC_GPLL0_EVEN, 3, 0, 0),
+	F(202000000, CFG_CLK_SRC_GPLL9, 4, 0, 0),
+	{ }
+};
+
+static const struct pll_vote_clk gpll9_vote_clk = {
+	.status = APCS_GPLL9_STATUS,
+	.status_bit = BIT(31),
+	.ena_vote = APCS_GPLLX_ENA_REG,
+	.vote_bit = BIT(8),
+};
+
 static ulong sc7280_set_rate(struct clk *clk, ulong rate)
 {
 	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
@@ -154,6 +175,13 @@ static ulong sc7280_set_rate(struct clk *clk, ulong rate)
 		clk_rcg_set_rate_mnd(priv->base, UFS_PHY_UNIPRO_CORE_CLK_CMD_RCGR,
 				     freq->pre_div, freq->m, freq->n, freq->src, 8);
 		return freq->freq;
+	case GCC_SDCC2_APPS_CLK:
+		freq = qcom_find_freq(ftbl_gcc_sdcc2_apps_clk_src, rate);
+		if (freq->src == CFG_CLK_SRC_GPLL9)
+			clk_enable_gpll0(priv->base, &gpll9_vote_clk);
+		clk_rcg_set_rate_mnd(priv->base, SDCC2_APPS_CLK_CMD_RCGR,
+				     freq->pre_div, freq->m, freq->n, freq->src, 8);
+		return freq->freq;
 	default:
 		return rate;
 	}

---
base-commit: 527115ef6783cec49e5610c523c124b399011361
change-id: 20260819-sc7280-sdcc2-clk-0b8f139508f7

Best regards,
-- 
Balaji Selvanathan <[email protected]>