[PATCH v2 2/3] clk: qcom: sc7280: use GATE_CLK_POLLED for CBCR-backed gate clocks

Convert the USB3, UFS, and SDCC gate clocks in the sc7280 gate clock
table from GATE_CLK() to GATE_CLK_POLLED(), so their enable status is
polled against the per-clock CBCR register instead of assuming the
enable write completed immediately.

Leave the PHY-sourced clocks unpolled: the USB3 pipe clock and the UFS
TX/RX symbol clocks are driven by the QMP PHY, not GCC, so their CBCR
only clears CLK_OFF once the PHY is up. Polling them at GCC enable time
would time out.

Signed-off-by: Balaji Selvanathan <[email protected]>
---
Changes in v2:
- keep the USB3 pipe and UFS TX/RX symbol clocks as unpolled GATE_CLK;
  their CBCR only clears CLK_OFF after the QMP PHY starts
---
 drivers/clk/qcom/clock-sc7280.c | 56 +++++++++++++++++++++--------------------
 1 file changed, 29 insertions(+), 27 deletions(-)

diff --git a/drivers/clk/qcom/clock-sc7280.c b/drivers/clk/qcom/clock-sc7280.c
index 91e3fcc27cb..70b80db6cac 100644
--- a/drivers/clk/qcom/clock-sc7280.c
+++ b/drivers/clk/qcom/clock-sc7280.c
@@ -160,22 +160,23 @@ static ulong sc7280_set_rate(struct clk *clk, ulong rate)
 }
 
 static const struct gate_clk sc7280_clks[] = {
-	GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0xf07c, 1),
-	GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0xf010, 1),
-	GATE_CLK(GCC_AGGRE_USB3_PRIM_AXI_CLK, 0xf080, 1),
-	GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0xf018, 1),
-	GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0xf01c, 1),
-	GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0xf054, 1),
-	GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0xf058, 1),
-	GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0xf05c, 1),
-	GATE_CLK(GCC_CFG_NOC_USB3_SEC_AXI_CLK, 0x9e07c, 1),
-	GATE_CLK(GCC_USB30_SEC_MASTER_CLK, 0x9e010, 1),
-	GATE_CLK(GCC_AGGRE_USB3_SEC_AXI_CLK, 0x9e080, 1),
-	GATE_CLK(GCC_USB30_SEC_SLEEP_CLK, 0x9e018, 1),
-	GATE_CLK(GCC_USB30_SEC_MOCK_UTMI_CLK, 0x9e01c, 1),
-	GATE_CLK(GCC_USB3_SEC_PHY_AUX_CLK, 0x9e054, 1),
-	GATE_CLK(GCC_USB3_SEC_PHY_COM_AUX_CLK, 0x9e058, 1),
-	GATE_CLK(GCC_PCIE_CLKREF_EN, 0x8c004, 1),
+	GATE_CLK_POLLED(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0xf07c, BIT(0), 0xf07c),
+	GATE_CLK_POLLED(GCC_USB30_PRIM_MASTER_CLK, 0xf010, BIT(0), 0xf010),
+	GATE_CLK_POLLED(GCC_AGGRE_USB3_PRIM_AXI_CLK, 0xf080, BIT(0), 0xf080),
+	GATE_CLK_POLLED(GCC_USB30_PRIM_SLEEP_CLK, 0xf018, BIT(0), 0xf018),
+	GATE_CLK_POLLED(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0xf01c, BIT(0), 0xf01c),
+	GATE_CLK_POLLED(GCC_USB3_PRIM_PHY_AUX_CLK, 0xf054, BIT(0), 0xf054),
+	GATE_CLK_POLLED(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0xf058, BIT(0), 0xf058),
+	GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0xf05c, BIT(0)),
+	GATE_CLK_POLLED(GCC_CFG_NOC_USB3_SEC_AXI_CLK, 0x9e07c, BIT(0), 0x9e07c),
+	GATE_CLK_POLLED(GCC_USB30_SEC_MASTER_CLK, 0x9e010, BIT(0), 0x9e010),
+	GATE_CLK_POLLED(GCC_AGGRE_USB3_SEC_AXI_CLK, 0x9e080, BIT(0), 0x9e080),
+	GATE_CLK_POLLED(GCC_USB30_SEC_SLEEP_CLK, 0x9e018, BIT(0), 0x9e018),
+	GATE_CLK_POLLED(GCC_USB30_SEC_MOCK_UTMI_CLK, 0x9e01c, BIT(0), 0x9e01c),
+	GATE_CLK_POLLED(GCC_USB3_SEC_PHY_AUX_CLK, 0x9e054, BIT(0), 0x9e054),
+	GATE_CLK_POLLED(GCC_USB3_SEC_PHY_COM_AUX_CLK, 0x9e058, BIT(0), 0x9e058),
+	GATE_CLK_POLLED(GCC_PCIE_CLKREF_EN, 0x8c004, BIT(0), 0x8c004),
+
 	GATE_CLK(GCC_PCIE_1_PIPE_CLK, 0x52000, BIT(30)),
 	GATE_CLK(GCC_PCIE_1_AUX_CLK, 0x52000, BIT(29)),
 	GATE_CLK(GCC_PCIE_1_CFG_AHB_CLK, 0x52000, BIT(28)),
@@ -196,20 +197,21 @@ static const struct gate_clk sc7280_clks[] = {
 	GATE_CLK(GCC_QUPV3_WRAP0_S6_CLK, 0x52008, BIT(16)),
 	GATE_CLK(GCC_QUPV3_WRAP0_S7_CLK, 0x52008, BIT(17)),
 	GATE_CLK(GCC_QUPV3_WRAP1_S1_CLK, 0x52008, BIT(23)),
-	GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x77010, BIT(0)),
-	GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x770cc, BIT(0)),
-	GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x77018, BIT(0)),
-	GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x77064, BIT(0)),
-	GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x7705c, BIT(0)),
-	GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x7709c, BIT(0)),
+
+	GATE_CLK_POLLED(GCC_UFS_PHY_AXI_CLK, 0x77010, BIT(0), 0x77010),
+	GATE_CLK_POLLED(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x770cc, BIT(0), 0x770cc),
+	GATE_CLK_POLLED(GCC_UFS_PHY_AHB_CLK, 0x77018, BIT(0), 0x77018),
+	GATE_CLK_POLLED(GCC_UFS_PHY_ICE_CORE_CLK, 0x77064, BIT(0), 0x77064),
+	GATE_CLK_POLLED(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x7705c, BIT(0), 0x7705c),
+	GATE_CLK_POLLED(GCC_UFS_PHY_PHY_AUX_CLK, 0x7709c, BIT(0), 0x7709c),
 	GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x7701c, BIT(0)),
 	GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x77020, BIT(0)),
 	GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_1_CLK, 0x770b8, BIT(0)),
-	GATE_CLK(GCC_UFS_1_CLKREF_EN, 0x8c000, BIT(0)),
-	GATE_CLK(GCC_SDCC2_AHB_CLK, 0x14008, BIT(0)),
-	GATE_CLK(GCC_SDCC2_APPS_CLK, 0x14004, BIT(0)),
-	GATE_CLK(GCC_SDCC1_AHB_CLK,  0x75004, BIT(0)),
-	GATE_CLK(GCC_SDCC1_APPS_CLK, 0x75008, BIT(0)),
+	GATE_CLK_POLLED(GCC_UFS_1_CLKREF_EN, 0x8c000, BIT(0), 0x8c000),
+	GATE_CLK_POLLED(GCC_SDCC2_AHB_CLK, 0x14008, BIT(0), 0x14008),
+	GATE_CLK_POLLED(GCC_SDCC2_APPS_CLK, 0x14004, BIT(0), 0x14004),
+	GATE_CLK_POLLED(GCC_SDCC1_AHB_CLK,  0x75004, BIT(0), 0x75004),
+	GATE_CLK_POLLED(GCC_SDCC1_APPS_CLK, 0x75008, BIT(0), 0x75008),
 };
 
 static int sc7280_enable(struct clk *clk)

-- 
2.34.1