[PATCH v2 3/3] clk: qcom: qcs615: use GATE_CLK_POLLED for CBCR-backed gate clocks

Convert the USB3, display, and UFS gate clocks in the qcs615 gate
clock table from GATE_CLK() to GATE_CLK_POLLED(), so their enable
status is polled against the per-clock CBCR register instead of
assuming the enable write completed immediately.

Leave the PHY-sourced clocks unpolled: the USB3 pipe clock and the UFS
TX/RX symbol clocks are driven by the QMP PHY, not GCC, so their CBCR
only clears CLK_OFF once the PHY is up. Polling them at GCC enable time
would time out.

Signed-off-by: Balaji Selvanathan <[email protected]>
---
Changes in v2:
- keep the USB3 pipe and UFS TX/RX symbol clocks as unpolled GATE_CLK;
  their CBCR only clears CLK_OFF after the QMP PHY starts
---
 drivers/clk/qcom/clock-qcs615.c | 38 ++++++++++++++++++++------------------
 1 file changed, 20 insertions(+), 18 deletions(-)

diff --git a/drivers/clk/qcom/clock-qcs615.c b/drivers/clk/qcom/clock-qcs615.c
index 7b3fe49de9c..4c7686d4c8b 100644
--- a/drivers/clk/qcom/clock-qcs615.c
+++ b/drivers/clk/qcom/clock-qcs615.c
@@ -109,16 +109,17 @@ static ulong qcs615_set_rate(struct clk *clk, ulong rate)
 }
 
 static const struct gate_clk qcs615_clks[] = {
-	GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0xf078, BIT(0)),
-	GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0xf010, BIT(0)),
-	GATE_CLK(GCC_AGGRE_USB3_PRIM_AXI_CLK, 0xf07c, BIT(0)),
-	GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0xf014, BIT(0)),
-	GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0xf018, BIT(0)),
-	GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0xf050, BIT(0)),
-	GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0xf054, BIT(0)),
+	GATE_CLK_POLLED(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0xf078, BIT(0), 0xf078),
+	GATE_CLK_POLLED(GCC_USB30_PRIM_MASTER_CLK, 0xf010, BIT(0), 0xf010),
+	GATE_CLK_POLLED(GCC_AGGRE_USB3_PRIM_AXI_CLK, 0xf07c, BIT(0), 0xf07c),
+	GATE_CLK_POLLED(GCC_USB30_PRIM_SLEEP_CLK, 0xf014, BIT(0), 0xf014),
+	GATE_CLK_POLLED(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0xf018, BIT(0), 0xf018),
+	GATE_CLK_POLLED(GCC_USB3_PRIM_PHY_AUX_CLK, 0xf050, BIT(0), 0xf050),
+	GATE_CLK_POLLED(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0xf054, BIT(0), 0xf054),
 	GATE_CLK(GCC_USB3_PRIM_PHY_PIPE_CLK, 0xf058, BIT(0)),
-	GATE_CLK(GCC_USB3_PRIM_CLKREF_CLK, 0x8c014, BIT(0)),
-	GATE_CLK(GCC_AHB2PHY_WEST_CLK, 0x6a004, BIT(0)),
+	GATE_CLK_POLLED(GCC_USB3_PRIM_CLKREF_CLK, 0x8c014, BIT(0), 0x8c014),
+	GATE_CLK_POLLED(GCC_AHB2PHY_WEST_CLK, 0x6a004, BIT(0), 0x6a004),
+
 	GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x5200c, GCC_QUPV3_WRAP0_S0_CLK_ENA_BIT),
 	GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x5200c, GCC_QUPV3_WRAP0_S1_CLK_ENA_BIT),
 	GATE_CLK(GCC_QUPV3_WRAP0_S2_CLK, 0x5200c, GCC_QUPV3_WRAP0_S2_CLK_ENA_BIT),
@@ -131,18 +132,19 @@ static const struct gate_clk qcs615_clks[] = {
 	GATE_CLK(GCC_QUPV3_WRAP1_S3_CLK, 0x5200c, GCC_QUPV3_WRAP1_S3_CLK_ENA_BIT),
 	GATE_CLK(GCC_QUPV3_WRAP1_S4_CLK, 0x5200c, GCC_QUPV3_WRAP1_S4_CLK_ENA_BIT),
 	GATE_CLK(GCC_QUPV3_WRAP1_S5_CLK, 0x5200c, GCC_QUPV3_WRAP1_S5_CLK_ENA_BIT),
-	GATE_CLK(GCC_DISP_HF_AXI_CLK, 0xb038, BIT(0)),
-	GATE_CLK(GCC_DISP_AHB_CLK, 0xb032, BIT(0)),
+
+	GATE_CLK_POLLED(GCC_DISP_HF_AXI_CLK, 0xb038, BIT(0), 0xb038),
+	GATE_CLK_POLLED(GCC_DISP_AHB_CLK, 0xb032, BIT(0), 0xb032),
 	/* UFS clocks */
-	GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x77010, BIT(0)),
-	GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x770c0, BIT(0)),
-	GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x77014, BIT(0)),
-	GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x77040, BIT(0)),
-	GATE_CLK(GCC_UFS_PHY_ICE_CORE_CLK, 0x77044, BIT(0)),
+	GATE_CLK_POLLED(GCC_UFS_PHY_AXI_CLK, 0x77010, BIT(0), 0x77010),
+	GATE_CLK_POLLED(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x770c0, BIT(0), 0x770c0),
+	GATE_CLK_POLLED(GCC_UFS_PHY_AHB_CLK, 0x77014, BIT(0), 0x77014),
+	GATE_CLK_POLLED(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x77040, BIT(0), 0x77040),
+	GATE_CLK_POLLED(GCC_UFS_PHY_ICE_CORE_CLK, 0x77044, BIT(0), 0x77044),
 	GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x77018, BIT(0)),
 	GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x7701c, BIT(0)),
-	GATE_CLK(GCC_UFS_PHY_PHY_AUX_CLK, 0x77078, BIT(0)),
-	GATE_CLK(GCC_UFS_MEM_CLKREF_CLK, 0x8c000, BIT(0)),
+	GATE_CLK_POLLED(GCC_UFS_PHY_PHY_AUX_CLK, 0x77078, BIT(0), 0x77078),
+	GATE_CLK_POLLED(GCC_UFS_MEM_CLKREF_CLK, 0x8c000, BIT(0), 0x8c000),
 };
 
 static int qcs615_enable(struct clk *clk)

-- 
2.34.1