Re: [PATCH v1] x86/nSVM: Expose the FlushByASID CPU Capability to L1 guests

On 13.08.2026 16:56, Abdelkareem Abdelsaamad wrote:
> On the AMD platforms, the Xen hypervisor requires the FlushByASID CPU
> capability to support HVM nested virtualization (see start_nested_svm).
> Consequently, the L1 hypervisor must report FlushByASID CPU capability support
> when intercepting CPUID instruction for the CPU feature from the L2 guest to
> support nested virtualization levels beyond L1. Extend the exposed HVM CPU
> policy to surface this CPU feature support for the guests.

While the change makes sense, I have to admit that I consider it a stretch
to justify changes by multi-level nesting, when a single level of nesting
is in need of a lot of work to actually behave sensibly. Further, "to
support nested virtualization levels beyond L1" looks pretty Xen-centric:
Other hypervisors may permit this without the feature.

> While at it remove the dangling `exitinfo1 = ns_vmcb->exitinfo1;` assignment
> inside the nested exit handling of svm_vmexit_handler().

Unrelated adjustments to somewhat nearby or related code are generally
okay, but here you're touching a different file and entirely unrelated
code. I think the two changes want splitting.

> Signed-off-by: Abdelkareem Abdelsaamad <[email protected]>
> ---
> Testing:
>  - Using a locally developed XTF test to call cpuid_edx(0x8000000aU);
>    - without the change, EDX returns 0x4AB (the FlushByASID 6th bit is not
>      set).
>    - with the change, EDX returns 0x4EB (the FlushByASID 6th bit set).

And the CPUID test that XTF has wasn't suitable?

Finally: Can you please drop Roger's old email address that you still
had on Cc?

Jan