WG: STM32F103 Clock

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Von: Webmaster WE [mailto:[email protected]] 
Gesendet: Mittwoch, 14. Oktober 2015 16:15
An: 'Ethernut User Chat (English)'
Betreff: AW: [En-Nut-Discussion] STM32F103 Clock

Hi Uwe,

sorry fort he delay...

I added the following code to SetSysClock() in stm32f1_clk.c

uint32_t Multiplier = SYSCLK_FREQ / (PLLCLK_IN>>1);
	uint32_t DividerX2 = RCC_CFGR_PLLXTPRE;

	/* If half of HSE_VALUE is to small for reaching target frequency
	 * deactivate /2 divider. */
	if (Multiplier > 16) {
		DividerX2 = 0;
		Multiplier = SYSCLK_FREQ / PLLCLK_IN;
	}

	/* Check Limits */
	if (DividerX2) {
		if (((PLLCLK_IN>>1)*Multiplier) > 72000000UL) Multiplier--;
	}
	else {
		if ((PLLCLK_IN*Multiplier) > 72000000UL) Multiplier--;
	}

	/* Shift multiplier to corresponding RCC_CFGR register bits */
	Multiplier = ((Multiplier-2)&0xF)<<18;

AND

	RCC->CFGR |= Multiplier;

Achim


B.t.w. I requested you to point out more exactly what problems Clock setup
on F1 has and how you solved it. An answer is still pending.

Bye
-- 
Uwe Bonnes                bon-1JbLm1bU5j5ZIx36JBfelj3+ndqKAYMe9FMPySWZwLkb1SvskN2V4Q@public.gmane.org

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
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