Re: Java Memory Model and ParallelStream
Andrew Haley via Concurrency-interest <[email protected]>
| Newsgroups | gmane.comp.java.jsr.166-concurrency |
|---|---|
| Message-ID | <[email protected]> |
On 3/6/20 2:35 PM, Luke Hutchison wrote: > On Fri, Mar 6, 2020, 7:15 AM Andrew Haley <[email protected]> wrote: > >> The CPU *hardware* does this all the time. Few processors have a >> total store order: x86, which does, is the exception here. > > Well that gets at my core question: whether a computational barrier always > strictly enforces memory happens-before ordering across the barrier, i.e. > whether a computational barrier To answer that I'd need to be told what a "computational barrier" is. I have some guesses, but I think you should spell it out. > is always also a memory ordering barrier. > > If the CPU does not have a total store order, I could imagine cases where a > computational barrier does not enforce memory ordering. What am I missing? -- Andrew Haley (he/him) Java Platform Lead Engineer Red Hat UK Ltd. <https://www.redhat.com> https://keybase.io/andrewhaley EAC8 43EB D3EF DB98 CC77 2FAD A5CD 6035 332F A671 _______________________________________________ Concurrency-interest mailing list [email protected] http://cs.oswego.edu/mailman/listinfo/concurrency-interest