RE: endianness issues across cpu , pci-bridge and NIC

Hmmm,

Unless some nifty new endian technique has arisen lately which I am unaware of ... :-)

Why are you having the bridge enable for byte swapping?

If data coming across the bridge is say, a 4 character text string
such as "abcd", you've just mangled the data.

If, on the other hand, the data is a little endian 0x12345678,
and you looking at the data on a big-endian machine, then you will
see the data correctl.

BUT - the point is, a bridge has no knowledge, and should never
have knowledge of endian-ness. Endian-neww applies only to
data in context, NOT all the data all the time.

Which is why there are the "little-endian to native" and
"big endian to native" functions.


Or am I missing something new here?



****|  -----Original Message-----
****|  From: Ashish anand [mailto:[email protected]]
****|  Sent: Thursday, April 10, 2003 6:03 AM
****|  To: [email protected]
****|  Subject: [eepro100] endianness issues across cpu , 
****|  pci-bridge and NIC
****|  
****|  
****|  Hello,
****|  folowing is the system configuration in terms of endianness.
****|  
****|  1.cpu runs in big-endian mode.
****|  
****|  2.byte swapping enabled at pci-bridge for both io and mem access.
****|  
****|  3.in asm/io.h all the read's and write's use byte swapping before
****|  operation.
****|  
****|  now though i am able to read serial eeprom MAC address 
****|  and self test
****|  passses successfully , but card reports "transmit timed 
****|  out" (i have
****|  checked interrupt is well in place)
****|  
****|  i doubt my code to handle endianness for passing 
****|  pointers from driver
****|  across card.
****|  WHETHER BELOW CODE work for my system ( note the use of plain
****|  virt_to_bus(x) and bus_to_virt(x) ,i was guessing 
****|  adition cpu_to_le32
****|  before bus_to virt call)
****|  
****|  void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
****|                             dma_addr_t *dma_handle)
****|  {
****|          void *ret;
****|          int gfp = GFP_ATOMIC;
****|          int order = get_order(size);
****|          if (hwdev == NULL || hwdev->dma_mask != 0xffffffff)
****|                  gfp |= GFP_DMA;
****|          ret = (void *)__get_free_pages(gfp, order);
****|         if (ret != NULL) {
****|                  memset(ret, 0, size);
****|                  dma_cache_wback_inv(ret, PAGE_SIZE << order);
****|                  ret = KSEG1ADDR(ret);   /* use uncached 
****|  address */
****|                  *dma_handle = virt_to_bus(ret);
****|          }
****|  
****|  extern inline dma_addr_t pci_map_single(struct pci_dev 
****|  *hwdev, void *ptr,
****|                                          size_t size, int 
****|  direction)
****|  {
****|          if (direction == PCI_DMA_NONE)
****|                  BUG();
****|          dma_cache_wback_inv((unsigned long)ptr, size);
****|          return virt_to_bus(ptr);
****|  }
****|          return ret;
****|  }
****|  
****|  Best Regards,
****|  Ashish Anand
****|  
****|  
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