Re: Home Grown ActionTec Development Daughterboard

>I spent 10 years doing HDL design in Verilog making bleeding-edge" 
>full-custom chips, so I know the possibilities are endless with this

Excellent news - glad you're an expert in the area.  I know nothing about 
these devices other than they seem very attractive for a generic "do it all" 
expansion board.

>kind of thing.  I did not realize how cheap these FPGA's have gotten or 
>more importantly, there seem to be usable HDL design tools that are free!

If Digilent can sell a CoolRunner II - XC2C256 CPLD surface mounted on a 40 
pin DIP module carrier for $15 in single quantity, then the IC itself must 
be dirt cheap!

>I say leave the existing (cheap) UART/USB recovery logic in place so that 
>the Actiontec always can boot with a console present, and then

Yes!

>add a little more area to the existing PCB to support the Xilinx chip, and 
>then add something like a compact flash slot (or two).

....and other i/o possibilities, see below.

>  0x8: register for address bits 0-7 (R/W)
>  0x9: register for address bits 8-15 (R/W)
>  0xa: register for address bits 16-23 (R/W)
>  0xb: register for address bits 24-31 (R/W)
>  0xc: data register bits 0-7 (R/W)
>  0xd: data register bits 8-15 (R/W)
>  0xe: control/config/status register (R/W)
>  0xf: read/write data at current address

I like it!

However I'm not sure we want to consume all remaining 8 address locations, 
as we may want to leave a couple addresses for direct i/o to other "you 
decide it" logic in the FPGA/CPLD. (and can have them programmed in the 
device simultaneously)

So I suggest the "bus expansion" design should accomplish your idea with as 
few locations as possible.  For instance do we need all 32 address bits?  
Maybe 24 would be enough?  Does it really need the 0xf address?  That kind 
of thinking.  (I know you threw out a first pass design idea, and a good one 
at that :-)

As far as FPGA and CPLD goes, here is what I've read.

CPLD forever remembers last program, even through power cycles, until has 
new program downloaded.  Example is the CoolRunner II XC2C256.

FPGA must be reprogrammed after every power cycle.  Example is, like on Game 
Boy thingy, Spartan II XC2S50.

I read in some cases designs incorporating a FPGA may also incorporate a 
CPLD that does nothing more than program the FPGA after powerup.

These devices must have tradeoffs, but I'm not sure which would be more 
appropriate for our goals.

Before we "lay down copper" it would be nice if we could, as a group, 
coordinate what features goes into the Next Gen Actiontec Daughterboard 
(NGAD? :-).

I think that the interface to J5 is going to be very straightforward. (uart, 
usb pass-through, xilinx, JTAG to xilinx? - that's it)

However what we put on the outside world part of the xilinx can be any 
number of things.

I would like to have some generic I/O capability, and I like some of the 
other suggestions I've seen.  (USB master, etc)  If we put USB in the FPGA, 
I think I found a reference on opencores that said it would need a companion 
chip PHY?

Generic I/O ability to direct read / write without going through the "bus 
expander" thing would be preferable to me.

Ok, enough rambling for now.

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