Fwd: [Fwd: re altera memory controller]

It seems he has sent it by mistake to the wront email address.
Forwarded message below.


---------------------------- Original Message ----------------------------
Subject: re altera memory controller
From:    [email protected]
Date:    Wed, September 10, 2003 7:32 am
To:      [email protected]
--------------------------------------------------------------------------

the SCL and SDA lines on a DIMM are I2C serial bus that hooks to a small
memory device, the purpose of the memory device is to give the system all
the  configuration information about the memory (ras/cas address width,
latency, clock  speed). you can search the web for free control software.
Keep in mind that on  a sdram the control pins don't do what they are
labelled like they do on an  edo memory, they really are just a command
bus that the memory samples and  responds to one or more clocks later.
sdrams chipps are organized in banks of 4,  its sort of like you have 2
more address lines but the important difference is  that you can have all
four banks doing different things all at the same time  (precharge, read,
write, idle, row open). the micron memory specs are pretty  clear, you
might want to read through them. you should be able to get  information on
the dimm spec from www.jedec.org but basically its a wrapper for the
memory parts themselves plus info on the configuration memory and the
board layout. jay

-------------------------------------------------------

-- 
Mohamed Eldesoky
Handasa-Arabia Organization
http://www.handasarabia.org


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