[PATCH i-g-t v3 2/2] tests/intel/xe_prefetch_fault: add L2 prefetch fault subtests

Add L2 prefetch fault testing. When L1 cache policy is
set to uncached (UC), the prefetch bypasses LSC and is sourced from L2
instead.

Add a new shader gpgpu_shader__l2_prefetch_fault() that uses message
descriptor 0x49C00 (L1UC_L2C_L3UC, cache control value 4) instead of
the existing 0x99C00 (L1C_L2C_L3C, cache control value 9). Only bits
[19:16] of the descriptor differ.

Add two new subtests:
  - l2-prefetch-fault: validates L2 prefetch fault with unmapped address
    followed by hit-under-miss with mapped page
  - l2-prefetch-fault-svm: same as above but in SVM mode with HMM-backed
    CPU page table resolution

v2:
  - Include generated iga64 codes for the new shader to fix compilation
    failures (Kamil)

v3:
  - Drop the gpgpu_shader__l2_prefetch_fault helper and inline the shader
    generation directly into get_l2_prefetch_shader (Andrzej)
  - Simplify the assembly by removing handcrafted dependencies and using
    the standard load.ugm.d64t.a64.uc.ca.uc syntax (Andrzej)
  - Drop unnecessary IGA64_FLAGS define and GFX_VER >= 4000 check (Andrzej)
  - Remove overly verbose message descriptor comments (Andrzej)

Signed-off-by: Varun Gupta <[email protected]>
---
 tests/intel/xe_prefetch_fault.c               | 73 +++++++++++++++++++
 .../xe_prefetch_fault.c.gen.iga64_codes.c     | 17 ++++-
 2 files changed, 89 insertions(+), 1 deletion(-)

diff --git a/tests/intel/xe_prefetch_fault.c b/tests/intel/xe_prefetch_fault.c
index e86cd68d9..ce741d5b2 100644
--- a/tests/intel/xe_prefetch_fault.c
+++ b/tests/intel/xe_prefetch_fault.c
@@ -130,6 +130,43 @@ static struct gpgpu_shader *get_prefetch_shader(int fd)
 	return shader;
 }
 
+static struct gpgpu_shader *get_l2_prefetch_shader(int fd)
+{
+	struct gpgpu_shader *shader;
+	uint64_t addr = xe_canonical_va(fd, PREFETCH_ADDR);
+
+	igt_assert_f((addr & 0x7) == 0, "address must be aligned to QWord!\n");
+
+	shader = gpgpu_shader_create(fd);
+
+	/*
+	 * This shader can only be used when in efficient 64bit mode.
+	 * For a given arbitrary ppgtt virtual address, it raises an L2 prefetch fault
+	 * using load instruction with L1 uncached + L2 cached cache policy.
+	 * With L1 uncached, the prefetch bypasses LSC and is sourced from L2.
+	 */
+	emit_iga64_code(shader, xe_l2_prefetch_fault_prefetch, R"(
+#if GFX_VER >= 3500
+L0:
+// Set base address with scalar register
+(W)   mov (1)                s0.0<1>:ud                         ARG(0):ud
+(W)   mov (1)                s0.1<1>:ud                         ARG(1):ud
+
+// A64 offset
+(W)   mov (8)                r30.0<1>:uq                       0x0:uq
+
+// Prefetch operations are implemented using a NULL destination register.
+// L1 uncached forces the prefetch to bypass LSC, making L2 the fault source.
+// load.ugm.d64t.a64.uc.ca.uc [src0]
+(W)   sendg.ugm (1)          null         r30:1      null:0     s0.0        0x49C00
+#endif
+	)", lower_32_bits(addr), upper_32_bits(addr));
+
+	gpgpu_shader__eot(shader);
+
+	return shader;
+}
+
 /**
  * SUBTEST: prefetch-fault
  * Description: Validate L1 prefetch fault and hit-under-miss behavior with
@@ -140,6 +177,16 @@ static struct gpgpu_shader *get_prefetch_shader(int fd)
  * Description: Validate L1 prefetch fault and hit-under-miss behavior in SVM
  *		mode with L1 cached, L2 cached cache policy (fault source: LSC)
  * Run type: FULL
+ *
+ * SUBTEST: l2-prefetch-fault
+ * Description: Validate L2 prefetch fault and hit-under-miss behavior with
+ *		L1 uncached, L2 cached cache policy (fault source: L2)
+ * Run type: FULL
+ *
+ * SUBTEST: l2-prefetch-fault-svm
+ * Description: Validate L2 prefetch fault and hit-under-miss behavior in SVM
+ *		mode with L1 uncached, L2 cached cache policy (fault source: L2)
+ * Run type: FULL
  */
 static void test_prefetch_fault(int fd, struct drm_xe_engine_class_instance *hwe,
 				bool svm, get_shader_fn get_shader)
@@ -296,6 +343,32 @@ int igt_main()
 		}
 	}
 
+	igt_subtest_with_dynamic("l2-prefetch-fault") {
+		xe_for_each_engine(fd, hwe) {
+			if (hwe->engine_class == DRM_XE_ENGINE_CLASS_RENDER ||
+			    hwe->engine_class == DRM_XE_ENGINE_CLASS_COMPUTE) {
+				igt_dynamic_f("%s%d", xe_engine_class_string(hwe->engine_class),
+					      hwe->engine_instance)
+					test_prefetch_fault(fd, hwe, false,
+							    get_l2_prefetch_shader);
+			}
+		}
+	}
+
+	igt_subtest_with_dynamic("l2-prefetch-fault-svm") {
+		if (!svm_supported)
+			igt_skip("SVM not supported on this device, skipping.\n");
+		xe_for_each_engine(fd, hwe) {
+			if (hwe->engine_class == DRM_XE_ENGINE_CLASS_RENDER ||
+			    hwe->engine_class == DRM_XE_ENGINE_CLASS_COMPUTE) {
+				igt_dynamic_f("%s%d", xe_engine_class_string(hwe->engine_class),
+					      hwe->engine_instance)
+					test_prefetch_fault(fd, hwe, true,
+							    get_l2_prefetch_shader);
+			}
+		}
+	}
+
 	igt_fixture() {
 		drm_close_driver(fd);
 	}
diff --git a/tests/intel/xe_prefetch_fault.c.gen.iga64_codes.c b/tests/intel/xe_prefetch_fault.c.gen.iga64_codes.c
index 0df7fe20e..5d387aa08 100644
--- a/tests/intel/xe_prefetch_fault.c.gen.iga64_codes.c
+++ b/tests/intel/xe_prefetch_fault.c.gen.iga64_codes.c
@@ -3,7 +3,22 @@
 
 #include "gpgpu_shader.h"
 
-#define MD5_SUM_IGA64_ASMS 153c8c0a5a3ed448d86f86bb51e8d140
+#define MD5_SUM_IGA64_ASMS 712da12709dd4ebfeffc82119c37c556
+
+struct iga64_template const iga64_code_xe_l2_prefetch_fault_prefetch[] = {
+	{ .gfx_ver = 3500, .size = 28, .code = (const uint32_t []) {
+		0x80000061, 0x60014220, 0x00000000, 0xc0ded000,
+		0x80000061, 0x60114220, 0x00000000, 0xc0ded001,
+		0x800c0061, 0x1e054330, 0x00000000, 0x00000000,
+		0x80012033, 0x00000004, 0xf0041e0c, 0x9c000000,
+		0x80000001, 0x00010000, 0x20000000, 0x00000000,
+		0x80000001, 0x00010000, 0x30000000, 0x00000000,
+		0x80000901, 0x00010000, 0x00000000, 0x00000000,
+	}},
+	{ .gfx_ver = 0, .size = 0, .code = (const uint32_t []) {
+
+	}}
+};
 
 struct iga64_template const iga64_code_xe_prefetch_fault_prefetch[] = {
 	{ .gfx_ver = 3500, .size = 28, .code = (const uint32_t []) {
-- 
2.43.0