[PATCH v4 2/3] dt-bindings: phy: rockchip-inno-csi-dphy: add rockchip,clk-lane-phase property
Gerald Loacker <[email protected]>
| Newsgroups | org.infradead.lists.linux-rockchip,org.infradead.lists.linux-arm-kernel,org.infradead.lists.linux-phy,org.kernel.vger.linux-devicetree,org.kernel.vger.linux-kernel |
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| Message-ID | <20260725-feature-mipi-csi-dphy-4k60-v4-2-5b2c4626d31e@wolfvision.net> |
Add support for the optional rockchip,clk-lane-phase device tree property to allow board-specific tuning of the clock lane sampling phase for improved signal integrity across supported data rates. Acked-by: Rob Herring (Arm) <[email protected]> Acked-by: Michael Riesch <[email protected]> Signed-off-by: Gerald Loacker <[email protected]> --- .../devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml b/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml index 03950b3cad08c..913aa688c0ae9 100644 --- a/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml +++ b/Documentation/devicetree/bindings/phy/rockchip-inno-csi-dphy.yaml @@ -56,6 +56,16 @@ properties: description: Some additional phy settings are access through GRF regs. + rockchip,clk-lane-phase: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 7 + default: 3 + description: + Clock lane sampling phase selection (hardware tap index 0–7). Each step + corresponds to an approximately 40 ps delay as described in the hardware + specification. + required: - compatible - reg -- 2.34.1 _______________________________________________ Linux-rockchip mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-rockchip